//-----------------------------------------------------------------------------
//  
//  Copyright (c) 2013
//
//  Project  : 
//  Module   : 
//  Parent   : 
//  Children : 
//
//  Description: 
//
//  Parameters:
//  Local Parameters:
//
//  Notes       : 
//
//  Multicycle and False Paths


module OH_RXOHCAP(
   input                      GTM_RXOH_RESET,

   input                      MPI_IN_CLOCK,
   input                      MPI_IN_RXOHCAP_START,
   input[10:0]                MPI_IN_RXOHCAP_ADDR,
   output[63:0]               MPI_OUT_RXOHCAP_RD,

   input                      RXCAP_IN_CLOCK,
   input[63:0]                RXCAP_IN_DATA,
   input[2:0]                 RXCAP_IN_FRM_FCNT8,
   input[8:0]                 RXCAP_IN_FRM_FCNT270,
   input[3:0]                 RXCAP_IN_FRM_FCNT9
   );


// capture start control

wire                          MPI_RXOHCAP_START;

wire                          ROWR_CLOCK;
reg[3:0]                      ROWR_TRIG_EDSREG;
reg                           ROWR_TRIG_START;
wire[63:0]                    ROWR_DATA;
wire[2:0]                     ROWR_FRM_FCNT8;
wire[8:0]                     ROWR_FRM_FCNT270;
wire[3:0]                     ROWR_FRM_FCNT9;
reg[6:0]                      ROWR_ROW_WORD_CNT72;
wire[3:0]                     ROWR_COL_BLOCK_CNT9;

reg[3:0]                      ROWR_FSM;
reg[10:0]                     ROWR_CLEAR_CNT2048;

reg[10:0]                     ROWR_RAM_ADDR;
reg                           ROWR_RAM_WEN;
reg[63:0]                     ROWR_RAM_DATA;

wire                          CAPM_CLKA, CAPM_CLKB;
wire                          CAPM_WEA;
wire[10:0]                    CAPM_ADDRA, CAPM_ADDRB;
wire[63:0]                    CAPM_DINA, CAPM_DOUTB;


  assign ROWR_CLOCK            = RXCAP_IN_CLOCK;
  assign MPI_RXOHCAP_START     = MPI_IN_RXOHCAP_START;
  assign ROWR_DATA[63:0]       = RXCAP_IN_DATA[63:0];
  assign ROWR_FRM_FCNT8[2:0]   = RXCAP_IN_FRM_FCNT8[2:0];
  assign ROWR_FRM_FCNT270[8:0] = RXCAP_IN_FRM_FCNT270[8:0];
  assign ROWR_FRM_FCNT9[3:0]   = RXCAP_IN_FRM_FCNT9[3:0];

// check the positive edge of capture start control
always @(posedge GTM_RXOH_RESET or posedge ROWR_CLOCK)begin
   if (GTM_RXOH_RESET==1'b1) begin
      ROWR_TRIG_EDSREG[3:0]                          <= 4'd0;
      ROWR_TRIG_START                                <= 1'b0;
   end
   else begin
      ROWR_TRIG_EDSREG[3:0]                          <= {ROWR_TRIG_EDSREG[2:0], MPI_RXOHCAP_START};
      ROWR_TRIG_START                                <= ROWR_TRIG_EDSREG[3]==1'b0 && ROWR_TRIG_EDSREG[2]==1'b1;
   end
end

always @(posedge GTM_RXOH_RESET or posedge ROWR_CLOCK)begin
   if (GTM_RXOH_RESET==1'b1)
      ROWR_ROW_WORD_CNT72[6:0]                       <= 7'd0;
   else begin
      if (ROWR_FRM_FCNT270[8:0]==9'd269 && ROWR_FRM_FCNT8[2:0]==3'd7)
         ROWR_ROW_WORD_CNT72[6:0]                    <= 7'd0;
      else if (ROWR_FRM_FCNT270[8:0]<9'd9)
         ROWR_ROW_WORD_CNT72[6:0]                    <= ROWR_ROW_WORD_CNT72[6:0] +7'd1;
   end
end
  assign  ROWR_COL_BLOCK_CNT9[3:0]    = ROWR_FRM_FCNT9[3:0];


always @(posedge GTM_RXOH_RESET or posedge ROWR_CLOCK)begin
   if (GTM_RXOH_RESET==1'b1)
      ROWR_FSM[3:0]                                  <= 4'd0;
   else begin
      case (ROWR_FSM[3:0])
      4'd0: begin
         if (ROWR_TRIG_START==1'b1)
            ROWR_FSM[3:0]                            <= 4'd1;
      end
      4'd1: begin
         if (ROWR_CLEAR_CNT2048[10:0]==11'd2047)
            ROWR_FSM[3:0]                            <= 4'd2;
      end
      4'd2: begin
         if (ROWR_FRM_FCNT8[2:0]==3'd7 && ROWR_FRM_FCNT270[8:0]==9'd269 && ROWR_FRM_FCNT9[3:0]==4'd8)
            ROWR_FSM[3:0]                            <= 4'd3;
      end
      4'd3: begin
         if (ROWR_FRM_FCNT8[2:0]==3'd7 && ROWR_FRM_FCNT270[8:0]==9'd269 && ROWR_FRM_FCNT9[3:0]==4'd8)
            ROWR_FSM[3:0]                            <= 4'd4;
      end
      4'd4: begin
            ROWR_FSM[3:0]                            <= 4'd0;
      end
      default: begin
            ROWR_FSM[3:0]                            <= 4'd0;
      end
      endcase
   end
end

always @(posedge GTM_RXOH_RESET or posedge ROWR_CLOCK)begin
   if (GTM_RXOH_RESET==1'b1)
      ROWR_CLEAR_CNT2048[10:0]                       <= 11'd0;
   else begin
      if (ROWR_FSM[3:0]==4'd1)
         ROWR_CLEAR_CNT2048[10:0]                    <= ROWR_CLEAR_CNT2048[10:0] +11'd1;
      else
         ROWR_CLEAR_CNT2048[10:0]                    <= 11'd0;
   end
end



always @(posedge GTM_RXOH_RESET or posedge ROWR_CLOCK)begin
   if (GTM_RXOH_RESET==1'b1) begin
      ROWR_RAM_ADDR[10:0]                                <= 10'd0;
      ROWR_RAM_WEN                                       <= 1'b0;
      ROWR_RAM_DATA[63:0]                                <= 64'd0;
   end
   else begin
      if (ROWR_FSM[3:0]==4'd1) begin
         ROWR_RAM_ADDR[10:0]                             <= ROWR_CLEAR_CNT2048[10:0];
         ROWR_RAM_WEN                                    <= 1'b1;
         ROWR_RAM_DATA[63:0]                             <= 64'd0;
      end
      else if(ROWR_FSM[3:0]==4'd3) begin
         ROWR_RAM_ADDR[10:0]                             <= {ROWR_COL_BLOCK_CNT9[3:0], ROWR_ROW_WORD_CNT72[6:0]};
         ROWR_RAM_WEN                                    <= ROWR_FRM_FCNT270[8:0]<9'd9;
         ROWR_RAM_DATA[63:0]                             <= ROWR_DATA[63:0];
      end
      else begin
         ROWR_RAM_ADDR[10:0]                             <= 11'd2047;
         ROWR_RAM_WEN                                    <= 1'b0;
         ROWR_RAM_DATA[63:0]                             <= 64'd0;
      end
   end
end


  assign   CAPM_CLKA                  = ROWR_CLOCK;
  assign   CAPM_WEA                   = ROWR_RAM_WEN;
  assign   CAPM_ADDRA[10:0]           = ROWR_RAM_ADDR[10:0];
  assign   CAPM_DINA[63:0]            = ROWR_RAM_DATA[63:0];

  assign   CAPM_CLKB                  = MPI_IN_CLOCK;
  assign   CAPM_ADDRB[10:0]           = MPI_IN_RXOHCAP_ADDR[10:0];
  assign   MPI_OUT_RXOHCAP_RD[63:0]   = CAPM_DOUTB[63:0];
OH_RXOHCAP_RAM128K_64_64          INST_CAPM128K_64_64(
   .CLKA                          (CAPM_CLKA),
   .WEA                           (CAPM_WEA),
   .ADDRA                         (CAPM_ADDRA[10:0]),
   .DINA                          (CAPM_DINA[63:0]),
   .CLKB                          (CAPM_CLKB),
   .ADDRB                         (CAPM_ADDRB[10:0]),
   .DOUTB                         (CAPM_DOUTB[63:0])
   );



endmodule
